The present invention is directed to integrated circuit design tools and, more particularly, to an electronic design automation tool for estimating capacitive cell load using electromigration analysis.
Integrated circuits (ICs) are designed using electronic design automation (EDA) tools. During the design flow, register-transfer-level (RTL) abstraction typically is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of the IC, selecting standard cell designs and their characteristics from a standard cell library. An RTL description is defined in terms of registers that store signal values, and combinational logic that performs logical operations on signal values. The RTL description is typically converted to a gate-level description (such as a netlist) that can then be used by placement and routing tools to create a physical layout.
The standard cell library contains look-up tables of variables of the different standard cells, for example input and output currents and voltages as a function of load impedances and the characteristics of the cells. In addition, the standard cell library contains look-up tables of minimum and maximum values of various parameters that should be enforced to avoid risk of functional failures of the cells, referred to as a Liberty file. The limiting values in the Liberty file take account of various process, operating voltage and temperature (PVT) variables and many different failure mechanisms.
Operational analog variables of the gate-level representation, like voltages, currents, rise and fall times and so on, can then be simulated using programs such as the Simulation Program with Integrated Circuit Emphasis (SPICE) and compared with limits defined by specifications for the cells.
Electromigration is a reliability phenomenon that is increasingly relevant to IC design as IC feature sizes are reduced without corresponding reductions in current levels in and between the cells and their loads, resulting in increased current density. Electromigration is caused by transfer of momentum from electrons to ions in a conductor, and can produce voids resulting in open circuit failure of the conductor, or growth of the conductor (whiskers or bumps) leading to short circuit with an adjacent conductor.
Electromigration is a function of the load on the output of the cell, and a limiting value of the load appears in the Liberty file. However the load current density causing possible electromigration failure is also a function of variables including the actual operating frequency, or pulse rise and fall times of the cell output voltage. It has been found that electromigration failure of a cell may occur at capacitive load values within the load limits indicated by the Liberty file.
It is possible to simulate and analyze the risks of electromigration using established calculations of the cells as a function of the voltages, load values and operating frequency, or pulse rise and fall times of the cells. However, calculating the maximum allowable load capacitance for all the cells in the IC design can be very calculation-intensive and time-consuming. Thus, it would be advantageous to have a method of doing so efficiently and with a higher degree of automation.